With advances of semiconductor technology and increasing of integration degree of integrated circuits (ICs), device dimensions are increasingly reduced. The increasingly reduced device dimensions often adversely affect device performance. For instance, as channel lengths are reduced to a certain level, short channel effects may occur. This often results in decrease of carrier mobility, increase of threshold voltage, and occurrence of drain induction barrier lower (DIBL).
In a conventional MOS fabrication process, a lightly doped source/drain (LDD) process and a halo implantation process are usually employed to form S/D regions of a semiconductor transistor in order to suppress the short channel effect.
FIGS. 1-3 depict a conventional method for forming a MOS transistor. Referring to FIG. 1, a semiconductor substrate 10 is provided. A gate structure 20 is formed on the semiconductor substrate 10. The gate structure 20 includes a gate dielectric layer 21 on the surface of the semiconductor substrate 10 and a gate 22 on the surface of the gate dielectric layer 21.
Referring to FIG. 2, an offset spacer 23 is formed on surface of sidewalls of the gate structure 20. A light ion implantation process is conducted using the offset spacer 23 and the gate structure 20 as a mask to form lightly doped regions 31 in the semiconductor substrate 10 on both sides of the gate structure 20. A halo implantation region 32 can be formed by a halo ion implantation surrounding the lightly doped region 31.
Referring to FIG. 3, a sidewall spacer 24 is formed on surface of the offset spacer 23. The semiconductor substrate 10 is then etched to form a groove therein using the gate structure 20, the offset spacer 23, and the sidewall spacer 24 as an etch mask. When a PMOS transistor is to be formed, a germanium-silicon layer is formed in the groove. When an NMOS transistor is to be formed, a silicon carbide layer is formed in the groove. A source/drain implantation process is then carried out to form source/drain 40.
However, use of conventional technology to form MOS transistors may cause source-drain punch-through effect and DIBL to occur, which adversely affects performance and reliability of the formed MOS transistors.